To date, most transistors used in power electronic applications have typically been fabricated with silicon (Si) semiconductor materials. Common transistor devices for power applications include Si CoolMOS, Si Power MOSFETs, and Si Insulated Gate Bipolar Transistors (IGBTs). While Si power devices are inexpensive, they suffer from a number of disadvantages, including relatively low switching speeds and high levels of electrical noise. More recently, silicon carbide (SiC) power devices have been considered due to their superior properties. III-N semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates to carry large currents, support high voltages and to provide very low on-resistance and fast switching times.
Most conventional III-N high electron mobility transistors (HEMTs) and related transistor devices are normally on, i.e., have a negative threshold voltage, which means that they can conduct current at zero gate voltage. These devices with negative threshold voltages are known as depletion-mode (D-mode) devices. It is preferable in power electronics to have normally off devices, i.e., devices with positive threshold voltages, that cannot conduct current at zero gate voltage, in order to avoid damage to the device or to other circuit components by preventing accidental turn on of the device. Normally off devices are commonly referred to as enhancement-mode (E-mode) devices.
Reliable fabrication and manufacturing of high-voltage III-N E-mode devices has thus far proven to be very difficult. One alternative to a single high-voltage E-mode device is to combine a high-voltage D-mode device with a low-voltage E-mode device in the configuration of FIG. 1 to form a hybrid device, which in many cases achieves the same or similar output characteristics as a single high-voltage E-mode device, shown in FIG. 2. The hybrid device of FIG. 1 includes a high-voltage D-mode transistor 23 and a low-voltage E-mode transistor 22 both encased in a package 10, the package including a source lead 11, a gate lead 12, and a drain lead 13. The source electrode of the low-voltage E-mode transistor 22 and the gate electrode of the high-voltage D-mode transistor 23 are both electrically connected to the source lead 11. The gate electrode of the low-voltage E-mode transistor 22 is electrically connected to the gate lead 12. The drain electrode of the high-voltage D-mode transistor 23 is electrically connected to the drain lead 13. The source electrode of the high-voltage D-mode transistor 23 is electrically connected to the drain electrode of the low-voltage E-mode transistor 22.
The device of FIG. 2 includes a single high-voltage E-mode transistor 21 encased in the same or a similar package to the hybrid device of FIG. 1. The source electrode of the high-voltage E-mode transistor 21 is connected to the source lead 11, the gate electrode of the high-voltage E-mode transistor 21 is connected to the gate lead 12, and the drain electrode of the high-voltage E-mode transistor 21 is connected to the drain lead 13. Both of the devices in FIGS. 1 and 2 are capable of blocking high voltages between the source lead 11 and drain lead 13 when 0V is applied to the gate lead 12 relative to the source lead 11, and both devices can conduct current from the source lead 11 to the drain lead 13 when a sufficiently positive voltage is applied to the gate lead 12 relative to the source lead 11. While there are many conventional applications in which the hybrid device of FIG. 1 can be used in place of the single high-voltage E-mode device of FIG. 2, there are certain applications in which modifications and/or improvements to the structure of the hybrid device are necessary in order to achieve the desired output.